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| MCP3002 2.7V Dual Channel 10-Bit A/D Converter with SPITM Serial Interface Features * * * * * * * * * * 10-bit resolution 1 LSB max DNL 1 LSB max INL Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPITM serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 200 ksps max sampling rate at VDD = 5V 75 ksps max sampling rate at VDD = 2.7V Low power CMOS technology: - 5 nA typical standby current, 2 A max - 550 A max. active current at 5V Industrial temp range: -40C to +85C 8-pin MSOP, PDIP, SOIC and TSSOP packages Package Types MSOP, PDIP, SOIC, TSSOP CS/SHDN CH0 CH1 VSS 1 2 3 4 8 7 6 5 VDD/VREF CLK DOUT DIN Functional Block Diagram VDD VSS MCP3002 * * Applications * * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems CH0 CH1 Input Channel Mux DAC Comparator Sample and Hold Control Logic 10-Bit SAR Description The Microchip Technology Inc. MCP3002 is a successive approximation 10-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3002 is programmable to provide a single pseudodifferential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are both specified at 1 LSB. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 200 ksps at 5V and 75 ksps at 2.7V. The MCP3002 device operates over a broad voltage range (2.7V - 5.5V). Low current design permits operation with a typical standby current of 5 nA and a typical active current of 375 A. The MCP3002 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Shift Register CS/SHDN DIN CLK DOUT (c) 2007 Microchip Technology Inc. DS21294C-page 1 MCP3002 1.0 1.1 ELECTRICAL CHARACTERISTICS Maximum Ratings* PIN FUNCTION TABLE Name Function VDD/VREF CH0 CH1 CLK DIN DOUT CS/SHDN VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied .....-65C to +125C ESD protection on all pins (HBM)........................> 4kV *Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. +2.7V to 5.5V Power Supply and Reference Voltage Input Channel 0 Analog Input Channel 1 Analog Input Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input ELECTRICAL CHARACTERISTICS All parameters apply at VDD = 5V, TAMB = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB = 25C unless otherwise noted. PARAMETER Conversion Rate: Conversion Time Analog Input Sample Time tCONV tSAMPLE -- -- 1.5 10 clock cycles clock cycles 200 75 ksps ksps VDD = 5V VDD = 2.7V SYM MIN TYP MAX UNITS CONDITIONS Throughput Rate DC Accuracy: Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance: Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Analog Inputs: Input Voltage Range for CH0 or CH1 in Single-Ended Mode Input Voltage Range for IN+ In pseudo-differential Mode Input Voltage Range for IN- In pseudo-differential Mode Leakage Current Switch Resistance Sample Capacitor Note 1: 2: fSAMPLE -- -- 10 INL DNL -- -- -- -- THD SINAD SFDR -- -- -- VSS IN+ ININVSS-100 -- RSS CSAMPLE -- -- 0.5 0.25 -- -- -76 61 78 -- -- -- 0.001 1K 20 1 1 1.5 1 -- -- -- VDD VDD+INVSS+100 1 -- -- bits LSB LSB LSB LSB dB dB dB V VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz No missing codes over temperature mV A pF See Figure 4-1 See Figure 4-1 This parameter is established by characterization and not 100% tested. The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK 10 kHz for temperatures at or above 70C. DS21294C-page 2 (c) 2007 Microchip Technology Inc. MCP3002 ELECTRICAL CHARACTERISTICS (CONTINUED) All parameters apply at VDD = 5V, TAMB = -40C to +85C, fSAMPLE = 200 ksps and fCLK = 16*fSAMPLE unless otherwise noted. Typical values apply for VDD = 5V, TAMB = 25C unless otherwise noted. PARAMETER Digital Input/Output: Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters: Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements: Operating Voltage Operating Current Standby Current Temperature Ranges: Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistance: Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-TSSOP Note 1: 2: JA JA JA JA -- -- -- -- 85 163 206 124 -- -- -- -- C/W C/W C/W C/W TA TA TA -40 -40 -65 -- -- -- +85 +85 +150 C C C VDD IDD IDDS 2.7 -- -- -- -- 525 300 0.005 5.5 650 -- 2 V A A VDD = 5.0V, DOUT unloaded VDD = 2.7V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF -- -- 140 140 100 -- -- -- -- -- -- 310 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.2 1.2 -- -- -- 50 50 125 200 125 200 100 -- 100 100 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 See Test Circuits, Figure 1-2 Note 1 VDD = 5V (Note 2) VDD = 2.7V (Note 2) VIH VIL VOH VOL ILI ILO CIN, COUT Straight Binary 0.7 VDD -- 4.1 -- -10 -10 -- -- -- -- -- -- -- -- -- 0.3 VDD -- 0.4 10 10 10 V V V V A A pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz SYM MIN TYP MAX UNITS CONDITIONS This parameter is established by characterization and not 100% tested. The sample cap will eventually lose charge, especially at elevated temperatures, therefore fCLK 10 kHz for temperatures at or above 70C. (c) 2007 Microchip Technology Inc. DS21294C-page 3 MCP3002 tCSH CS tSUCS tHI CLK tSU DIN tHD tLO MSB IN tEN tDO NULL BIT MSB OUT tR tF LSB tDIS DOUT FIGURE 1-1: Serial Timing. Load circuit for tDIS and tEN Test Point VDD 3 k Test Point DOUT CL = 30 pF 30 pF VSS 3 k tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Load circuit for tR, tF, tDO 1.4V DOUT VDD/2 Voltage Waveforms for tR, tF VOH VOL tR tF CLK DOUT Voltage Waveforms for tEN DOUT CS 1 2 3 4 B9 tEN Voltage Waveforms for tDO CS CLK tDO DOUT Voltage Waveforms for tDIS VIH 90% tDIS DOUT Waveform 2 10% DOUT Waveform 1* * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits. (c) 2007 Microchip Technology Inc. DS21294C-page 4 MCP3002 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 0.6 0.4 0.6 0.4 VDD = 2.7V INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 0 25 Positive INL 0.2 0.0 -0.2 -0.4 -0.6 Positive INL Negative INL Negative INL 50 75 100 125 150 175 200 225 250 0 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: Rate. Integral Nonlinearity (INL) vs. Sample FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 1.0 0.8 0.6 0.4 VDD = 5V fSAMPLE = 200 ksps 1.0 0.8 0.6 0.4 VDD = 2.7V fSAMPLE = 75 ksps INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 Digital Code Digital Code FIGURE 2-2: Integral Nonlinearity (INL) vs. Code. FIGURE 2-5: (VDD = 2.7V). Integral Nonlinearity (INL) vs. Code 0.5 0.4 0.3 0.2 Positive INL 0.5 0.4 0.3 0.2 VDD = 2.7V fSAMPLE = 75 ksps Positive INL INL (LSB) INL (LSB) Negative INL 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 50 75 100 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25 0 25 50 75 100 Negative INL Temperature (C) Temperature (C) FIGURE 2-3: Temperature. Integral Nonlinearity (INL) vs. FIGURE 2-6: Integral Nonlinearity Temperature (VDD = 2.7V). (INL) vs. (c) 2007 Microchip Technology Inc. DS21294C-page 5 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 1.0 0.8 0.6 0.4 Positive INL 0.8 0.6 0.4 Positive DNL DNL (LSB) INL(LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Negative INL All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps 0.2 0.0 -0.2 -0.4 -0.6 -0.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Negative All points taken at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps VDD (V) VDD (V) FIGURE 2-7: Integral Nonlinearity (INL) vs. VDD. FIGURE 2-10: Differential Nonlinearity (DNL) vs. VDD. 0.6 0.4 0.6 VDD = 2.7V 0.4 DNL (LSB) Positive DNL 0.0 -0.2 -0.4 -0.6 0 25 50 75 100 125 150 175 200 225 250 Negative DNL DNL (LSB) 0.2 0.2 0.0 -0.2 -0.4 -0.6 0 Positive DNL Negative DNL 25 50 75 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Sample Rate. Nonlinearity (DNL) vs. FIGURE 2-11: Differential Sample Rate (VDD = 2.7V). Nonlinearity (DNL) vs. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = 5V fSAMPLE = 200 ksps 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 128 256 384 512 640 768 896 1024 VDD = 2.7V fSAMPLE = 75 ksps DNL (LSB) Digital Code DNL (LSB) Digital Code FIGURE 2-9: Differential Nonlinearity Code (Representative Part). (DNL) vs. FIGURE 2-12: Differential Nonlinearity Code (Representative Part, VDD = 2.7V). (DNL) vs. DS21294C-page 6 (c) 2007 Microchip Technology Inc. MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 0.4 0.3 0.2 Positive DNL 0.4 VDD = 2.7V 0.3 0.2 fSAMPLE = 75 ksps DNL (LSB) 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 Negative DNL DNL (LSB) Positive DNL 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 Negative DNL Temperature (C) Temperature (C) FIGURE 2-13: Differential Temperature. Nonlinearity (DNL) vs. FIGURE 2-16: Differential Temperature (VDD = 2.7V). Nonlinearity (DNL) vs. 1.0 0.8 All points taken at fSAMPLE = 200 ksps except 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD = 2.7V, fSAMPLE = 75 ksps 1.0 All points taken at fSAMPLE = 200 ksps except 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD = 2.7V, fSAMPLE = 75 ksps Gain Error (LSB) VDD (V) Offset Error (LSB) VDD (V) FIGURE 2-14: Gain Error vs. VDD. FIGURE 2-17: Offset Error vs. VDD. 0.0 -0.1 -0.2 -0.3 VDD = 5V -0.4 -0.5 -50 -25 0 25 50 75 100 fSAMPLE = 200 ksps VDD = 2.7V fSAMPLE = 75 ksps 0.8 0.7 Offset Error (LSB) Gain Error (LSB) 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 -25 0 25 50 75 100 VDD = 2.7V fSAMPLE = 75 ksps VDD = 5V fSAMPLE = 200 ksps Temperature (C) Temperature (C) FIGURE 2-15: Gain Error vs. Temperature. FIGURE 2-18: Offset Error vs. Temperature. (c) 2007 Microchip Technology Inc. DS21294C-page 7 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 80 70 60 80 VDD = 5V 70 60 fSAMPLE = 200 ksps SNR (dB) 50 40 30 20 10 0 1 10 100 VDD = 2.7V fSAMPLE = 75 ksps VDD = 5V fSAMPLE = 200 ksps SINAD (dB) 50 40 30 20 10 0 1 10 100 VDD = 2.7V fSAMPLE = 75 ksps Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-19: Signal to Noise Ratio (SNR) vs. Input Frequency. FIGURE 2-22: Signal to Noise and Distortion (SINAD) vs. Input Frequency. 0 -10 -20 80 70 VDD = 5V fSAMPLE = 200 ksps SINAD (dB) -30 THD (dB) V DD = 2.7V fSAMPLE = 75 ksps 60 50 40 30 20 -40 -50 -60 -70 -80 -90 -100 1 V DD = 5V fSAMPLE = 200 ksps 10 100 10 0 -40 -35 VDD = 2.7V fSAMPLE = 75 ksps -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-20: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Signal Level. 10.0 9.9 10.0 9.5 9.8 ENOB (rms) ENOB 9.7 9.6 9.5 9.4 2.5 3.0 3.5 4.0 4.5 5.0 5.5 All points at fSAMPLE = 200 ksps except VDD = 2.7V, fSAMPLE = 75 ksps 9.0 V DD = 2.7V fSAMPLE = 75 ksps 8.5 V DD = 5V fSAMPLE = 200 ksps 8.0 1 10 100 VDD (V) Input Frequency (kHz) FIGURE 2-21: Effective number of bits (ENOB) vs. VDD. FIGURE 2-24: Effective Number of Bits (ENOB) vs. Input Frequency. DS21294C-page 8 (c) 2007 Microchip Technology Inc. MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 100 90 80 70 V DD = 5V fSAMPLE = 200 ksps 600 500 400 SFDR (dB) 60 50 40 30 20 10 0 1 10 100 VDD = 2.7V fSAMPLE = 75 ksps IDD (A) 300 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 All points at fCLK = 3.2 MHz except at V DD = 2.5V, fCLK = 1.2 MHz Input Frequency (kHz) VDD (V) FIGURE 2-25: Spurious Free (SFDR) vs. Input Frequency. Dynamic Range FIGURE 2-28: IDD vs. VDD. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 20000 40000 VDD = 5V fSAMPLE = 200 ksps fINPUT = 10.976 kHz 4096 points 600 550 500 450 400 350 300 250 200 150 100 50 0 10 Amplitude (dB) IDD (A) VDD = 5V V DD = 2.7V 60000 80000 100000 100 1000 10000 Frequency (Hz) Clock Frequency (kHz) FIGURE 2-26: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-29: IDD vs. Clock Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 VDD = 2.7V fSAMPLE = 75 ksps fINPUT = 1.00708 kHz 4096 points 600 500 400 V DD = 5V fCLK = 3.2 MHz Amplitude (dB) IDD (A) 300 200 100 0 VDD = 2.7V fCLK = 1.2 MHz 5000 10000 15000 20000 25000 30000 35000 -50 -25 0 25 50 75 100 Frequency (Hz) Temperature (C) FIGURE 2-27: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). FIGURE 2-30: IDD vs. Temperature. (c) 2007 Microchip Technology Inc. DS21294C-page 9 MCP3002 Note: Unless otherwise indicated, VDD = 5V, fSAMPLE = 200 ksps, fCLK = 16* fSAMPLE,TA = 25C 70 2.0 Analog Input Leakage (nA) CS = VDD 60 50 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 V DD = 5V IDDS (pA) 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -25 0 25 50 75 100 VDD (V) Temperature (C) FIGURE 2-31: IDDS vs. VDD. FIGURE 2-33: Analog Input leakage current vs. Temperature. 100.00 VDD = CS = 5V 10.00 IDDS (nA) 1.00 0.10 0.01 -50 -25 0 25 50 75 100 Temperature (C) FIGURE 2-32: IDDS vs. Temperature. DS21294C-page 10 (c) 2007 Microchip Technology Inc. MCP3002 3.0 3.1 PIN DESCRIPTIONS CH0/CH1 Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 for information on programming the channel configuration. of the command string transmitted to the device. The IN+ input can range from IN- to the reference voltage, VDD. The IN- input is limited to 100 mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 10-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the 3FFh code will not be seen unless the IN+ input level goes above VDD level. If the voltage at IN+ is equal to or greater than {[VDD + (IN-)] - 1 LSB}, then the output code will be 3FFh. 3.2 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.3 Serial Clock (CLK) The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. 3.4 Serial Data Input (DIN) The SPI port serial data input pin is used to clock in input channel configuration data. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. 4.0 DEVICE OPERATION The MCP3002 A/D converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 10-bit digital output code. Conversion rates of 200 ksps are possible on the MCP3002. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI compatible interface. 4.2 Digital Output Code The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3002, VDD is used as the reference voltage. V REF LSB Size = ------------1024 As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. 1024*V IN Digital Output Code = -----------------------V DD where: VIN = analog input voltage VDD = supply voltage 4.1 Analog Inputs The MCP3002 device offers the choice of using the analog input channels configured as two single-ended inputs that are referenced to VSS or a single pseudo-differential input. The configuration setup is done as part of the serial command before each conversion begins. When used in the psuedo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part (c) 2007 Microchip Technology Inc. DS21294C-page 11 MCP3002 VDD VT = 0.6V Sampling Switch SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT ILEAKAGE SS RS CSAMPLE RSS CHx VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 4-1: Analog Input Model. 4.0 Clock Frequency (MHz) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 100 1000 VDD = 2.7V fSAMPLE = 75 ksps V DD = 5V fSAMPLE = 200 ksps 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21294C-page 12 (c) 2007 Microchip Technology Inc. MCP3002 5.0 5.1 SERIAL COMMUNICATIONS Overview Communication with the MCP3002 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in psuedo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low, will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. Table 5-1 shows the configuration bits for the MCP3002. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 10 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 10 data bits have been transmitted and the device continues to receive clocks while the CS is held low (and the MSBF bit is high), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3002 devices with hardware SPI ports. If it is desired, the CS can be raised to end the conversion period at any time during the transmission. Faster conversion rates can be obtained by using this technique if not all the bits are captured before starting a new cycle. Some system designers use this method by capturing only the highest order 8 bits and `throwing away' the lower 2 bits. TABLE 5-1: Configuration Bits for the MCP3002. CONFIG BITS SGL/ DIFF SINGLE ENDED MODE PSEUDODIFFERENTIAL MODE ODD/ SIGN CHANNEL SELECTION 0 1 GND 1 1 0 0 0 1 0 1 + + IN+ INININ+ - (c) 2007 Microchip Technology Inc. DS21294C-page 13 MCP3002 tCYC tCSH CS tSUCS CLK tCYC ODD/ SIGN SGL/ DIFF DIN Start Don't Care ODD/ SIGN DOUT HI-Z tSAMPLE MS BF Null B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Bit tCONV HI-Z tDATA** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator powers down while the reference input becomes a high impedance node. FIGURE 5-1: Communication with the MCP3002 using MSB first format only. tCYC tCSH CS tSUCS CLK Power Down SGL/ DIFF ODD/ SIGN MSBF Start DIN Don't Care DOUT HI-Z tSAMPLE Null B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7* B8 B9 Bit HI-Z (MSB) tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator powers down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3002 using LSB first format. DS21294C-page 14 (c) 2007 Microchip Technology Inc. MCP3002 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3002 with Microcontroller (MCU) SPI Ports with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the `high' state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains one leading zero before the start bit. Arranging the leading zero this way produces the output 10 bits to fall in positions easily manipulated by the MCU. When the first 8 bits are transmitted to the device, the MSB data bit is clocked out of the A/D Converter on the falling edge of clock number 6. After the second eight clocks have been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending `leading zeros' before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 62 show how the MCP3002 can be interfaced to a MCU CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges SGL/ DIFF ODD/ SIGN MSBF SCLK Start DIN Don't Care DOUT Start Bit X 1 NULL B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X SGL/ ODD/ MSBF X DIFF SIGN X X X 0 (Null) B9 X X X X X X X X X X X B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-1: SPI Communication with the MCP3002 using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of A/D Converter on falling edges SGL/ DIFF ODD/ SIGN SCLK DIN MSBF Start Don't Care DOUT HI-Z NULL B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) Start Bit X 1 SGL/ ODD/ MSBF X DIFF SIGN X X X X X X X X X X X X X X 0 X (Null) B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don't Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-2: SPI Communication with the MCP3002 using 8-bit segments (Mode 1,1: SCLK idles high). (c) 2007 Microchip Technology Inc. DS21294C-page 15 MCP3002 6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations When the MCP3002 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample cap for 700 s at VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at VDD = 2.7V, the time it takes to transmit the 1.5 clocks for the sample period and the 10 clocks for the actual conversion must not exceed 700 s. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1 F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D converters, refer to AN-688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back in to the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive, filter, and gain the analog input of the MCP3002. This amplifier provides a low impedance output for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistors values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD Device 4 Device 1 Device 3 Device 2 10 F R1 C1 R2 C2 R3 R4 MCP601 + ININ+ MCP3002 1 F VIN FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. FIGURE 6-3: Typical (2 pole Active Filter). Anti-Aliasing Filter Circuit DS21294C-page 16 (c) 2007 Microchip Technology Inc. MCP3002 7.0 7.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP3002 I/PNNN e3 0725 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP3002 ISN e3 0726 NNN 8-Lead MSOP XXXXXX YWWNNN Example: 3002I e3 725NNN 8-Lead TSSOP XXXX YYWW NNN Example: 3002 e3 0725 NNN Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. DS21294C-page 17 MCP3002 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 D 3 E A2 A A1 e b1 b L c eB Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .348 .115 .008 .040 .014 - MIN INCHES NOM 8 .100 BSC - .130 - .310 .250 .365 .130 .010 .060 .018 - .210 .195 - .325 .280 .400 .150 .015 .070 .022 MAX .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS21294C-page 18 (c) 2007 Microchip Technology Inc. MCP3002 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h c h A A2 A1 L L1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN MILLMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B (c) 2007 Microchip Technology Inc. DS21294C-page 19 MCP3002 8-Lead Plastic Micro Small Outline Package (MS) [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b A A2 c e A1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c L1 MILLIMETERS MIN NOM 8 0.65 BSC - 0.75 0.00 - 0.85 - 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0 0.08 0.60 0.95 REF - - 8 0.23 0.80 1.10 0.95 0.15 MAX L Lead Width b 0.22 - 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-111B DS21294C-page 20 (c) 2007 Microchip Technology Inc. MCP3002 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 b 2 e c A A2 A1 L1 L Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Footprint Foot Angle Lead Thickness N e A A2 A1 E E1 D L L1 c 0 0.09 4.30 2.90 0.45 - 0.80 0.05 MIN MILLIMETERS NOM 8 0.65 BSC - 1.00 - 6.40 BSC 4.40 3.00 0.60 1.00 REF - - 8 0.20 4.50 3.10 0.75 1.20 1.05 0.15 MAX Lead Width b 0.19 - 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-086B (c) 2007 Microchip Technology Inc. DS21294C-page 21 MCP3002 NOTES: DS21294C-page 22 (c) 2007 Microchip Technology Inc. MCP3002 APPENDIX A: REVISION HISTORY Revision C (January 2007) This revision includes updates to the packaging diagrams. (c) 2007 Microchip Technology Inc. DS21294C-page 23 MCP3002 NOTES: DS21294C-page 24 (c) 2007 Microchip Technology Inc. MCP3002 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) MCP3002-I/P: Industrial Temperature, PDIP package. b) Device: MCP3002: 10-Bit Serial A/D Converter MCP3002T: 10-Bit Serial A/D Converter (Tape and Reel) (SOIC and TSSOP only) MCP3002-I/SN: Industrial Temperature, SOIC package. MCP3002-I/ST: Industrial Temperature, TSSOP package. MCP3002-I/MS: Industrial Temperature, MSOP package. c) d) Temperature Range: I = -40C to +85C Package: MS P SN ST = = = = Plastic Micro Small Outline (MSOP), 8-lead Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic TSSOP (4.4 mm), 8-lead (c) 2007 Microchip Technology Inc. DS21294C-page25 MCP3002 NOTES: DS21294C-page 26 (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. DS21294C-page 27 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS21294C-page 28 (c) 2007 Microchip Technology Inc. |
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